Digital VLSI
ADVANCED
Digital VLSI Design
The complete digital design track (Weeks 9–20): static & alternative logic, layout, delay modelling, power, sequential design, RTL-to-GDSII physical design, signoff, DFT and a final project reviewed by an external expert.
Led by Er. Deepak Mishra · 8 students · 24 lessons
Curriculum
Week 9: Static CMOS Logic & Alternative Logic
- 🔒 Static CMOS Logic & Alternative Logic — OverviewReading
- 🔒 Static CMOS Logic & Alternative Logic — Lecture--:--
Week 10: Digital Layout Design
- 🔒 Digital Layout Design — OverviewReading
- 🔒 Digital Layout Design — Lecture--:--
Week 11: Delay Modelling
- 🔒 Delay Modelling — OverviewReading
- 🔒 Delay Modelling — Lecture--:--
Week 12: Elmore Delay & Logical Effort
- 🔒 Elmore Delay & Logical Effort — OverviewReading
- 🔒 Elmore Delay & Logical Effort — Lecture--:--
Week 13: CMOS Power Analysis
- 🔒 CMOS Power Analysis — OverviewReading
- 🔒 CMOS Power Analysis — Lecture--:--
Week 14: Sequential Circuit Design
- 🔒 Sequential Circuit Design — OverviewReading
- 🔒 Sequential Circuit Design — Lecture--:--
Week 15: Registers, Counters & FSMs
- 🔒 Registers, Counters & FSMs — OverviewReading
- 🔒 Registers, Counters & FSMs — Lecture--:--
Week 16: RTL Design & Logic Synthesis
- 🔒 RTL Design & Logic Synthesis — OverviewReading
- 🔒 RTL Design & Logic Synthesis — Lecture--:--
Week 17: Physical Design
- 🔒 Physical Design — OverviewReading
- 🔒 Physical Design — Lecture--:--
Week 18: Signoffs
- 🔒 Signoffs — OverviewReading
- 🔒 Signoffs — Lecture--:--
Week 19: Design for Testability (DFT)
- 🔒 Design for Testability (DFT) — OverviewReading
- 🔒 Design for Testability (DFT) — Lecture--:--
Week 20: Final Digital Design Project
- 🔒 Final Digital Design Project — OverviewReading
- 🔒 Final Digital Design Project — Lecture--:--
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